(1) Field of the Invention
The present invention relates to a multiprocessor control system, and a boot device and a boot control device used in the multiprocessor control system, the multiprocessor control system including a plurality of processors on a board.
(2) Description of the Related Art
A multiprocessor control system in which a plurality of processors are provided on a board is known. With recent development of device and architecture technology, processors have advanced in speed and integration. Systems and devices utilizing processors now require an increase of processing speed, advanced functions, an increase of the number of multiplexed channels and an increase of application programs used.
Basically, a multiprocessor control system includes a plurality of processors, and the processors have application programs necessary for their operation. The application programs are retained in an external storage, such as a floppy disk, a read-only memory, a communication board or the like. To boot one of the processors, the application program for the processor is read from the external storage and loaded to the processor.
FIG. 1 shows a conventional multiprocessor control system. In the conventional multiprocessor control system of FIG. 1, a processor (PROCESSOR#1) 1, a processor (PROCESSOR#2) 2, . . . , and a processor (PROCESSOR#N) 3 (where N is an integer) are provided, and a plurality of buses 7, 8, 9 are individually provided for the processors 1, 2, 3. The processors 1, 2, 3 require a plurality of memories 4, 5, 6 in which application programs necessary for the operation of the processors 1, 2, 3 are stored therein. The processors 1, 2, 3 require a plurality of control devices 10, 11, 12 which control boot of the processors 1, 2, 3, respectively. The bus 7 interconnects the processor 1 and the memory 4, the bus 8 interconnects the processor 2 and the memory 5, and the bus 9 interconnects the processor 3 and the memory 6.
FIG. 2 shows another conventional multiprocessor control system. In the conventional multiprocessor control system of FIG. 2, a processor (PROCESSOR#1) 1, a processor (PROCESSOR#2) 2, . . . , and a processor (PROCESSOR#N) 3, a plurality of memories 4, 5, 6, a bus arbiter 27, and shared buses 28 and 29 are provided. The memories 4, 5, 6 store application programs (which will be called boot data) necessary for the operation of the processors 1, 2, 3, respectively. The shared buses 28 and 29 interconnect the processors 1, 2, 3, the memories 4, 5, 6, and the bus arbiter 27.
The bus arbiter 27 controls bus access of the processors 1, 2, 3 to the shared buses 28 and 29 by determining which processor can actively use the shared buses 28 and 29. When a bus use factor occurs in one of the processors 1, 2, 3, the processor of concern outputs a request to the bus arbiter 27. When the buses 28 and 29 can be used, the bus arbiter 27 sends an acknowledge to the processor of concern. The processor of concern receives the acknowledge, and is able to access the buses 28 and 29. The boot data (the application program necessary for the operation of the processor) is read from one of the memories 4, 5, 6 by using the busses 28 and 29, and loaded to the processor of concern.
FIG. 3 shows a bus access processing of the multiprocessor control system of FIG. 2. As shown in FIG. 3, when a bus use factor (18) occurs in the processor (PROCESSOR#1) 1, the processor 1 outputs a request to the bus arbiter 27 (S0). When the buses 28 and 29 are currently not used by the other processors, the bus arbiter 27 sends an acknowledge to the processor 1 (S1). The processor 1 receives the acknowledge, and obtains the ability to access the buses 28 and 29. The boot data is read from the memory 4 by using the buses 28 and 29, and loaded to the processor 1 (20). After the bus access is complete, the processor 1 outputs an access complete to the bus arbiter 27 (S2). The processor 1 requires a waiting time (19) after the output of the request to the bus arbiter 27 and before the receipt of the acknowledge from the bus arbiter 27.
When a bus use factor (24) occurs in the processor (PROCESSOR#2) 2, the processor 2 outputs a request to the bus arbiter 27 (S3). When the buses 28 and 29 are currently not used by another processor, the bus arbiter 27 sends an acknowledge to the processor 2 (S5). The processor 2 receives the acknowledge, and obtains the ability to access the buses 28 and 29. The boot data is read from the memory 5 by using the buses 28 and 29, and loaded to the processor 2 (26). After the bus access is complete, the processor 2 outputs an access complete to the bus arbiter 27 (S6). In the meantime, after the output of the request by the processor 2, the processor 1 outputs a request to the bus arbiter 27 (S4). As the buses 28 and 29 are used by the processor 2, the bus arbiter 27 does not send an acknowledge to the processor 1 until the bus access by the processor 2 is complete. In this case, the processor 1 requires a longer waiting time (22) after the output of the request to the bus arbiter 27 and before the receipt of the acknowledge from the bus arbiter 27. After the bus complete from the processor 2 is received (S6), the bus arbiter 27 sends an acknowledge to the processor 1 (S7). The processor 1 receives the acknowledge, and obtains the ability to access the buses 28 and 29 (23).
In the conventional multiprocessor control system of FIG. 2, the bus arbiter 27 sends an acknowledge to the processor of concern when the buses 28 and 29 are not used by another processor. However, when the buses 28 and 29 are used by another processor, the bus arbiter 27 does not send an acknowledge to the processor of concern. The processor of concern is held in a waiting condition until the bus access by the other processor is complete and an acknowledge from the bus arbiter 27 is received. The waiting time in the latter case is longer than the waiting time in the former case. In a certain case, the processor which outputs a secondary request after the output of the request by another processor, has to perform an abort process to cancel the bus access.
In addition, in the above-described multiprocessor control system, the processors must output a request to the bus arbiter 27 (S0, S3 or S4) and receive an acknowledge from the bus arbiter 27 (S1, S5 or S7) in order to start the bus access. In a case of the multiprocessor control system including a large number of processors, the overhead of the processors when starting the bus access is considerably increased, and the congestion of the bus access between the processors is likely to occur. In a case of the multiprocessor control system having a swap function of the application programs, the time to boot one of the processors and start the application program for the processor is considerably increased as the number of the processors increases. Accordingly, it is desirable to provide a multiprocessor control system which can reduce the time to boot one of the processors by using a simple circuit structure.
An object of the present invention is to provide an improved multiprocessor control system in which the above-mentioned problems are eliminated.
Another object of the present invention is to provide a multiprocessor control system which can speedily boot one of the processors by using a simple, scale-down configuration, and shorten the overall starting time of the application program for the processor.
Still another object of the present invention is to provide a boot control device which can speedily boot one of the processors by using a simple, scale-down configuration, and shorten the overall starting time of the application program for the processor.
A further object of the present invention is to provide a boot device which can speedily boot one of the processors by using a simple, scale-down configuration, and shorten the overall starting time of the application program for the processor.
The above-mentioned objects of the present invention are achieved by a multiprocessor control system including a plurality of processors, a boot control device controlling boot of the plurality of processors, a storage device storing boot data therein, and a shared bus interconnecting the plurality of processors, the boot control device and the storage device, the plurality of processors constituting at least one boot processor to which the boot data is to be loaded, the boot control device including: a time slot division unit which produces time slots on the shared bus by multiplexing channels for the plurality of processors; and a time sharing control unit which determines a time slot for the boot processor among the time slots produced by the time slot division unit, and assigns the time slot to the boot processor, the time sharing control unit comprising: a processor interface part which notifies a time-slot location of the time slot determined by the time sharing control unit, to the boot processor; and a bus time-slot setting part which notifies the time-slot location to the storage device, the bus time-slot setting part allowing reading of the boot data from the storage device and inserting of the boot data into the time slot at the time-slot location among the time slots on the shared bus, so that the boot data is loaded into the boot processor via the shared bus.
The above-mentioned objects of the present invention are achieved by a boot control device which controls boot of a plurality of processors connected to a shared bus, the plurality of processors constituting at least one boot processor to which boot data is to be loaded, including: a time slot division unit which produces time slots on the shared bus by multiplexing channels for the plurality of processors; and a time sharing control unit which determines a time slot for the boot processor among the time slots produced by the time slot division unit, and assigns the time slot to the boot processor, the time sharing control unit comprising: a processor interface part which notifies a time-slot location of the time slot determined by the time sharing control unit, to the boot processor; and a bus time-slot setting part which notifies the time-slot location to the storage device, the bus time-slot setting part allowing reading of the boot data from the storage device and inserting of the boot data into the time slot at the time-slot location among the time slots on the shared bus, so that the boot data is loaded into the boot processor via the shared bus.
The above-mentioned objects of the present invention are achieved by a boot device including a board on which a plurality of processors, a boot control device controlling boot of the processors, a storage device storing boot data, and a shared bus interconnecting the plurality of processors, the boot control device and the storage device, are installed, the plurality of processors constituting at least one boot processor to which the boot data is to be loaded, the boot control device including: a time slot division unit which produces time slots on the shared bus by multiplexing channels for the plurality of processors; and a time sharing control unit which determines a time slot for the boot processor among the time slots produced by the time slot division unit, and assigns the time slot to the boot processor, the time sharing control unit comprising: a processor interface part which notifies a time-slot location of the time slot determined by the time sharing control unit, to the boot processor; and a bus time-slot setting part which notifies the time-slot location to the storage device, the bus time-slot setting part allowing reading of the boot data from the storage device and inserting of the boot data into the time slot at the time-slot location among the time slots on the shared bus, so that the boot data is loaded into the boot processor via the shared bus.
In the multiprocessor control system of a preferred embodiment of the present invention, the boot control device includes the time sharing control unit which determines a time slot for the boot processor among the time slots produced by the time slot division unit, and assigns the time slot to the boot processor, and the time sharing control unit includes the bus time-slot setting part which notifies the time-slot location to the storage device, the bus time-slot setting part allowing reading of the boot data from the storage device and inserting of the boot data into the time slot at the time-slot location among the time slots on the shared bus, so that the boot data is loaded into the boot processor via the shared bus. The boot control device according to the present invention provides an integrated boot control of the plurality of processors by using the shared bus and provides a simple, scale-down circuit structure on the periphery of the plurality of processors. The boot control device of the present invention is effective in speedily booting one of the processors by using a simple, scale-down configuration, and effective in shortening the overall starting time of the application program for the processor of concern.
The boot device of a preferred embodiment of the present invention can speedily boot one of the processors by using a simple, scale-down configuration, and can shorten the overall starting time of the application program for the processor of concern. In the boot device of the present invention, the plurality of processors, the boot control device, the storage device and the shared bus are installed on the board. The boot device of the present invention is effective in using a simple, scale-down circuit structure.